DataIO ------------------------------------------ -- Version 0x0D 7 05 01 0 (5/1/07) -- - Added ability to disable channels (channels are skipped) as follows: -- - Bits 5:0 of Control Register 1 (0x00000C) are used as individual channel-enables: -- Bit 0 : Mezz Card 1, Channel 1 -- Bit 1 : Mezz Card 1, Channel 2 -- Bit 2 : Mezz Card 1, Channel 3 -- Bit 3 : Mezz Card 2, Channel 1 -- Bit 4 : Mezz Card 2, Channel 2 -- Bit 5 : Mezz Card 2, Channel 3 -- - A bit value of '1' enables the channel. -- - The power-up setting of this register is all 1s (all channels enabled) -- - After changing the value of this register, the FPGA should be reset before taking any data. -- Otherwise, the state machines that merge the data may end up in the wrong state. -- -- Version 0x0D 7 05 14 0 (5/14/07) -- - Added logic to transmit the 7-bit word counts for each channel to the Control FPGA for inclusion -- in the data stream (2 words are sent for each event) -- - Added a FIFO (Buffer_Number_FIFO) to store the L2 buffer number until after the EOE signal -- - Word count format is as follows (WC* = word count for channel *): -- Bits: 31:30 29:23 22:16 15:14 13:7 6:0 -- Word 1: 0 0 WC3 WC2 0 0 WC1 WC0 -- Word 2: 0 0 0000000 0000000 0 0 WC5 WC4 -- - Two new strobes (using ports UD_ctrlspare0 and UD_ctrlspare1) are used for these 2 words -- - Word 1 is sent on the clock cycle immediately after the 2nd EOE word -- - Word 2 is sent on the clock cycle immediately after Word 1 -- - Only the resepective new strobes (UD_ctrlspare0 for Word 1 and UD_ctrlspare1 for Word 2) -- are valid during transmission of these words; the normal data strobe *must* be invalid -- - All word counts sent to the Control FPGA are zeroed out for disabled channels Control ------------------------------------------ -- Version 0x0C 7 05 02 0 (5/2/07) -- - Added the ability to abort an event based on a signal sent from the Tracklist Pulsar -- - Aborting an event results in an SLINK packet containing only 1 data word: 0xC000C000 -- - Added Abort_Event_Logic_0 to store these abort bits -- - On an L1A, the bit mask in Tracklist A is used to generate a single bit that determines -- whether or not that event should be aborted. That bit is then sent over 3 separate pairs -- of LVDS lines, along with data strobes, to the 3 XFT boards. These are the pin mappings: -- - Tracklist Control A - TS_Out connector -- Data 1: pins 35 & 36 -- Strobe 1: pins 37 & 38 -- Data 2: pins 43 & 44 -- Strobe 2: pins 45 & 46 -- Data 3: pins 49 & 50 -- Strobe 3: pins 51 & 52 -- - Control XFT Merger - TS_In connector -- Data: pins 35 & 36 -- Strobe: pins 37 & 38 -- - The Control XFT Merger firmware waits for this abort bit before sending any data over the -- SLINK connection. If the abort bit is a '0', the data packet is sent as usual. If it's -- a '1', then a single-word SLINK packet is sent with the data word set to 0xC000C000. -- - To use this version of the firmware, the Tracklist board must be connected, or else -- no data will be transmitted -- -- Version 0x0C 7 05 17 0 (5/17/07) -- - Added logic to receive the 7-bit word counts for each channel from the DataIO FPGAs for inclusion -- in the data stream (two 32-bit words are sent for each event) -- - Added Word_Count_Storage_0 to store the word counts in FIFOs -- - Word count format from each DataIO FPGA is as follows (WC* = word count for channel *): -- Bits: 31:30 29:23 22:16 15:14 13:7 6:0 -- Word 1: 0 0 WC3 WC2 0 0 WC1 WC0 -- Word 2: 0 0 0000000 0000000 0 0 WC5 WC4 -- - Four new strobes (using ports LD1_ctrlspare0, LD1_ctrlspare1, LD2_ctrlspare0, -- and LD2_ctrlspare1) are used -- - Five states were added to DataIOFIFOmerger (FIFOMergerSM) to append the word counts at the end -- of the data stream -- - Output data format (WC* = word count for Finder *): -- Bits: 31:30 29:23 22:16 15:14 13:7 6:0 -- Word 1: 0 0 WC3 WC2 0 0 WC1 WC0 -- Word 2: 0 0 WC7 WC6 0 0 WC5 WC4 -- Word 3: 0 0 WC11 WC10 0 0 WC9 WC8 -- - Changed the EOE logic surrounding the DataIOFIFOmerger (FIFOMergerSM) so that the state machine -- now produces the EOE signal -- -- Version 0x0C 7 06 06 0 (6/6/07) -- - Added the ability to ignore the abort event logic -- - Bit 0 of Control Register 2 (0x000018) in the VME Interface determines if the aborts are ignored: -- Bit 0 = 0: do not ignore event aborts -- Bit 0 = 1: ignore any event aborts -- - Added the ignore_abort_event port to the VMEInterface -- - Added the ignore_abort_event internal signal to the main Control_XFTmerger design -- - Added the ignore_abort_event port to the DataIOFIFOmerger -- - Changed 2 of the DataIOFIFOmerger state transitions to include ignore_abort_event -- - WARNING: the FPGA should be reset if bit 0 of Control Register 2 is reset to 0 -- -- Version 0x0C 7 07 23 0 (7/23/07) -- - Added the ability to detect if an event will overflow the FILAR FIFOs and truncate that event if so -- - Added the FILAR_Overflow_Detection component -- - Rerouted the data strobe from the DataIOFIFOmerger (FIFOMergerSM) so it passes through -- FILAR_Overflow_Detection before going to the SlinkInputFIFO -- - Added sending_wc and clear_overflow_reg to the DataIOFIFOmerger (FIFOMergerSM) component -- - Control Register 3 is now used for storing the delay for clearing the word counts in the -- FILAR_Overflow_Detection, and also for storing the maximum number of words that can be sent -- before an overflow is triggered: -- Bits 11:0 - number of timer ticks to clear a word count (each tick is 12.5 ns) -- Bits 25:16 - word count maximum before overflow occurs (should be a little less than 512) -- - Added the ability to receive the abort signal from the P2 backplane connector (in addition to the -- TS_In connector) -- - Redefined XFT_abort_event to be XFT_abort_event_0 and XFT_abort_strobe to be XFT_abort_strobe_0 -- - Added XFT_abort_event_1 and XFT_abort_strobe_1 and connected them to ports r_Pulsar_freeze_n -- and r_Pulsar_spare_n, respectively -- - Added the paths for XFT_abort_event_1 and XFT_abort_strobe_1 to the Abort_Event_Logic -- - Added logic to combine the abort_event signals and the strobe signals so that the correct path -- is always chosen (either from a cable or the backplane) -- - Fixed a bug: the overflow bit was sometimes not cleared properly when ignoring aborted events -- - Added an overflow clear (clear_overflow_reg) to the DataIOFIFOmerger (FIFOMergerSM) component -- during check1_state -- - Fixed a bug: an extra eoe pulse was sent by the DataIOFIFOmerger (FIFOMergerSM) component -- - Added an internal eoe signal to DataIOFIFOmerger and masked it with the strobe_mask -- - Fixed a bug: no data words were sent for an aborted event with overflow -- - Modified the sending_wc signal in the DataIOFIFOmerger (FIFOMergerSM) component so it's also -- high during the abort_word1_state and the abort_word2_state -- - Redefined the SLINK error bits -- - Changed bits 15:2 to all zeros -- - Defined bit 1 as the FILAR overflow bit (set to '1' if event was truncated) -- - Defined bit 0 as the abort bit (set to '1' if event was aborted) -- - Redefined the abort signal pins so the signals come in on TS_OUT(0) and TS_OUT(1) instead of -- TS_IN(2) and TS_IN(3) -- Old Mapping New Mapping -- ----------- ----------- -- data: TS_IN(2)+ = pin 35 data: TS_OUT(0)+ = pin 3 -- data_n: TS_IN(2)- = pin 36 data_n: TS_OUT(0)- = pin 4 -- strobe: TS_IN(3)+ = pin 37 strobe: TS_OUT(1)+ = pin 5 -- strobe_n: TS_IN(3)- = pin 38 strobe_n: TS_OUT(1)- = pin 6 -- ----------- ----------- -- TS_IN(2) = L2A_from_proc_n TS_OUT(0) = GL2A_from_TS_n -- TS_IN(3) = L2R_from_proc_n TS_OUT(1) = GL2R_from_TS_n -- TS_IN_enable_n = '0' TS_OUT_enable_n = '1' -- -- Version 0x0C 7 08 02 0 (8/2/07) -- - Compiled using Leonardo Spectrum instead of Quartus -- -- Version 0x0C 7 08 17 0 (8/17/07) -- - Redefined the abort signal pins so the signals come in on TS_IN(2) and TS_IN(3) instead of -- TS_OUT(0) and TS_OUT(1) -- -- Version 0x0C 7 09 04 0 (9/4/07) -- - Changed the timers in FILAR_Overflow_Detection from 12 to 20 bits -- - Redefined Control Register 3 -- Bits 19:0 - number of timer ticks to clear a word count (each tick is 12.5 ns) -- Bits 29:20 - word count maximum before overflow occurs (should be a little less than 512) -- - Pipelined Timer_Cnt_0_Compare, Timer_Cnt_1_Compare, Timer_Cnt_2_Compare, and Timer_Cnt_3_Compare -- in the FILAR_Overflow_Detection component -- - Changed Abort_Event_FIFO in the Abort_Event_Logic component from an LPM_FIFO to -- a FIFO_SC_D1_W8_Reg component -- -- Version 0x0C 7 09 26 0 (9/26/07) -- - Added 2 VME registers for monitoring the state of the FILAR_Overflow_Detection component -- - Added State Register 1 (0x000024, read-only) -- Bits 31:30 - "00" -- Bits 29:20 - word count register 1 -- Bits 19:10 - word count register 0 -- Bits 9:0 - current word count -- - Added State Register 2 (0x000028, read-only) -- Bits 31:28 - "0000" -- Bit 27 - timer 3 enable -- Bit 26 - timer 2 enable -- Bit 25 - timer 1 enable -- Bit 24 - timer 0 enable -- Bits 23:22 - event count -- Bit 21 - total word count >= word count max -- Bit 20 - overflow bit -- Bits 19:10 - word count register 3 -- Bits 9:0 - word count register 2 -- -- Version 0x0C 7 10 09 0 (10/9/07) -- - Redefined the abort signal pins so the signals come in on TS_OUT(0) and TS_OUT(1) instead of -- TS_IN(2) and TS_IN(3) -- - Changed the power-up value of Control Register 2 from 0 to 1 -- - Changed the power-up value of Control Register 3 from 0 to -- 1072693264 = 0x3FF00010 => word count max = 1023, timer delay = 16 -- -- Version 0x0C 7 10 15 0 (10/15/07) -- - Added an AND gate to mask out abort_event with ignore_abort_event on the way into the -- FILAR_Overflow_Detection component so that the abort flag is not set when ignore_abort_event = '1' -- -- Version 0x0C 7 10 19 0 (10/19/07) -- - Added the ignore_abort_event signal (bit 0 of register 0x18) to bit 2 of the SLINK trailer word -- - Added input port ignore_abort_event to FILAR_Overflow_Detection -- - Moved the AND gate added in the last version inside the FILAR_Overflow_Detection component -- - Assigned ignore_abort_event to bit 2 of error_flags_data(15:0)