AXPR Address Map

Address   bits 
 1 (0x04)  8   write/read generic LINT CSR (**See Table 1**)
 2 (0x08)  3   write/read axial correlation bits pipeline depth
 3 (0x0C)  5   write/read axial correlation count pipeline depth
 4 (0x10)  5   write/read timestamp pipeline depth
 5 (0x14)  5   write/read timestamp control threshold bits
 6 (0x18)  3   write/read timestamp control wait bits
 7 (0x1C)  8   latch status bits on write cycle, read them on read cycle
 8 (0x20) 0/16 send latch to rb-chip on write cycle, read rb-chip on read cycle
 9 (0x24)  2   write/read the read-back select register (**See Table 2**)
10 (0x28) 16   write/read the "fake output data" register

Access Routines
Address   bits 
 1 (0x04)  8   void SetLintCsr(UINT32 data); UINT32 GetLintCsr();
 2 (0x08)  3   void SetACBPipeDepth(UINT32 data); UINT32 GetACBPipeDepth();
 3 (0x0C)  5   void SetACCPipeDepth(UINT32 data); UINT32 GetACCPipeDepth();
 4 (0x10)  5   void SetTSPipeDepth(UINT32 data); UINT32 GetTSPipeDepth();
 5 (0x14)  5   void SetTSCThreshBits(UINT32 data); UINT32 GetTSCThreshBits();
 6 (0x18)  3   void SetTSCWaitBits(UINT32 data); UINT32 GetTSCWaitBits();
 7 (0x1C)  8   
 8 (0x20) 0/16 
 9 (0x24)  2   
10 (0x28) 16   


Table 1: CSR bits [default 0]

Bit         Signal
----------|------------------------
0 (static)  axpr [enable] outputs
1 (static)  select [real]/fake output
2 (static)  spare
3 (static)  spare
4 (pulsed)  time_find reset
5 (pulsed)  spare
6 (pulsed)  spare
7 (pulsed)  spare


Table 2: Readback Bits

Select   Data[15..0]
-------|---------------
0        axout[15..0]
1        axout[31..16]
2        axout[47..32]
3        gnd[15..6],axtime[1..0],axcnt[3..0]