A small group of us within Fermilab interested in LC Vertex Detector R&D had a second small meeting on May 15th. We come from different backgrounds and expertise and have slightly different initial interests (technologies other than CCDs are also appealing). On the table, is to organize R&D efforts as they might be spelled out in either the NSF or DOE consortium proposals this Fall. Hopefully, we can use the Santa Cruz meeting to set an appropriate direction of the efforts. Before the Santa Cruz meeting, you mentioned having a group phone meeting to have preliminary discussions -- a good idea. Three areas in particular have been spelled out as R&D items needing the most attention for the LC Vertex Detector. 1) Thinned structures. 2) Radiation hardness studies. 3) Faster readout. We have resources available to address any or all three of these areas within the next year. But other commitments won't allow us to do everything -- so we'll need guidance on specifics on what can best help the American effort on LC vertex detector R&D. Specifically, on 1), we are already doing R&D on thinned sensors and read out chips associated with the BTeV pixel project. The main issue for this effort is protecting bump bonds for large 8" wafers being thinned down to 150-200 um. In this R&D, we have access to optical and touch probe measurement equipment and have used an optical fringe facility measurements at Argonne National Lab. We could inform the LC Vertex Detector group on our current efforts and measurements. We can initiate discussions with vendors to make test samples thinned below 100 um. A suggestion was also made that this might make a good SBIR topic. On 2), we routinely perform radiation measurements at a variety of facilities and could arrange for LC devices being exposed to Co-60, proton beams, sources, etc. One of us has had experience using the Lowell facility for 1 MeV neutron exposure. Fermilab is also working on establishing a supported test beam beginning towards the end of this year. On 3), we have operated silicon detectors and readouts under a variety of systems. Our FNAL ESE group has recently developed a PC based PCI card DAQ system that has a large programmable chip. This card is expected to be used as stand-alone DAQ for FPIX pixel chip readout and SVX4 silicon strip readout. Such a system could likely be configured to operate LC CCD or other technology test stands. Getting a system up and running would be an initial first step toward looking at other readout issues. Longer term, we have access to ASIC and sensor design experience. Those at Fermilab who have expressed some interest include: Harold Fox (D0, Northwestern Univ.) Christian Gingu (FNAL ASIC group) Simon Kwan (BTeV, FNAL Rad Hard Vertex Group) Ron Lipton (D0, FNAL) William Wester (CDF, FNAL ASIC group) |